Exegy, the high-performance trading solutions provider, in collaboration with AMD, has achieved a record-breaking actionable latency of up to 13.9 nanoseconds in the latest STAC-T0 report, which evaluates tick-to-trade network-I/O latency. The milestone was accomplished using an off-the-shelf solution (AMD Alveo’s UL3524 FPGA accelerator card) with an asynchronous implementation for the critical path of the algorithm and network stack. The achievement represents a 49% reduction in latency, marking the lowest tick-to-trade latency performance of any published STAC-T0 benchmark.
“It’s crucial for people to understand what we’re measuring, as context is important with such low numbers,” Olivier Cousin, Director of FGPA Solutions at Exegy, tells TradingTech Insight. “The STAC T0 report measures the latency of a system ingesting UDP and sending TCP frames. This covers the typical market data tick-to-order flow. The main value of this report lies in what is called ‘actionable latency,’ or reaction time. When a UDP frame contains a specific field, such as a price, which triggers an action, the clock starts only when that specific field (i.e. a price) enters the FPGA, not at the beginning of the UDP frame. We measure the time from this point until the TCP order exits the FPGA. With this benchmark, we are showcasing that the latency induced by the handling of 10Gbs Ethernet went from 24.2ns to 13.9ns with the new AMD card, which includes hardened MAC/PCS.”
Exegy claims to be the only capital markets technology provider offering a comprehensive FPGA development framework specifically tailored for ultra-low latency financial applications. Exegy’s nxFramework standardises the development of FPGA-based trading platforms, allowing developers to focus on optimising their core business logic. Exegy’s offering includes reference designs, expertise, and support, facilitating a faster time-to-production for firms developing ultra-low latency trading systems.
The production-proven FPGA development framework provides clients with reference designs to manage a wide range of applications, including pre-trade risk check gateways and tick-to-trade electronic trading platforms. The collaboration with AMD combines innovative hardware with production-tested applications, delivering groundbreaking performance through an off-the-shelf solution that ensures the lowest possible latency.
“There are two main innovations that contribute to this achievement,” says Cousin. “Typically, within an FPGA, there are resources that handle the 10 Gig connectivity. AMD’s innovation is their AMD Alveo UL3524 accelerator card, which involves hard-wiring the logic that deals with the 10 Gig protocol into the ASIC, rather the FPGA, which still has to manage all the network layers above Ethernet. This innovation is a contributing factor to the 49% latency reduction.”
He continues: “Exegy’s innovation lies in creating a UDP stack, TCP stack, and logic that processes the data and sends orders, all with zero latency in the FPGA. There are no clock cycles used for this critical path, achieving the absolute minimum latency as the FPGA processes the data in less than a clock cycle. Our nxFramework includes a full UDP stack for examining UDP traffic and a full TCP stack that supports the complete TCP protocol. For instance, if the exchange requests a TCP fragment to be resent, the TCP stack will resend it. The system is entirely self-contained and operates exclusively in hardware.”
The significant reduction in tick-to-trade execution latency underscores the success of Exegy’s partnership with AMD, which began last year, and demonstrates the company’s ongoing commitment to minimising latency. The collaboration leverages hardware acceleration, FPGA flexibility, and low-latency networking to ensure high performance and determinism. The Exegy team achieved precise testing measurements, reducing jitter to 200 picoseconds—up to 10 times lower than previous benchmarks—thus ensuring the accuracy of the STAC-T0 results. Existing Exegy customers, as part of their subscription, received updates to the IP cores that enabled this latency record.
“The value we demonstrate with this report is that the nxFramework highlights the lowest achievable latency with the FPGA technology currently available in the industry, and we assist our customers in attaining this performance,” says Cousin. “With the addition of support for this AMD card, customers can migrate their code with minimal development time. Customers using our nxFramework solution can purchase this card and migrate their design to systematically achieve the lowest possible latency.”
STAC benchmarks are the industry standard for evaluating solutions that enable high-speed analytics on time-series tick data. The STAC-T0 benchmark, which uses industry-standard hardware, making it fully transparent and reproducible, specifically assesses tick-to-trade network-I/O latency. The previous lowest benchmark speed of 24.2 nanoseconds was also achieved using AMD accelerators.
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